Compact Transistor Model-Based Low-Power CMOS Analog Circuit Design Methodology Using Particle Swarm Optimization

This work describes a compact transistor model-based low-power CMOS analog circuit design methodology using particle swarm optimization (PSO). The proposed approach replaces the actual transistor-level circuit with equations that represent the DC and AC characteristics and performance of the circuit block. As such, the optimization engine can directly use the equations to find the optimum design variables, including the transistor size (W, L) and operating conditions (ID, VGS, VDS). In this way, circuit simulation is not required for each optimization step, which leads to significant design time reduction. For concept validation, an actual design of a two-stage amplifier that meets the required performance for DC gain, GBW, PM, and slew rate under minimum power consumption using CMOS 65 nm technology has been performed, where the proposed design framework led to a DC gain of 67.13 dB, a GBW of 50.21 MHz, a PM of 58.08°, and a slew rate of 28.7 V/μs under power consumption of 45.39 μW with 16,000× and 1198× optimization time reduction compared to conventional PSO and parallel PSO.