The nonlinearity of the multi-level digital-to-analog converter (DAC), arising from element mismatches, is a critical issue in the design of multi-bit Delta-Sigma modulators (DSMs). In this brief, we propose an extremely linear multi-level DAC that requires no trimming, calibration, or dynamic element matching for continuous-time DSMs that are sensitive to loop delays. The proposed DAC combines a tri-level switched-capacitor circuit with a pulse-width-modulation (PWM) scheme modified to eliminate the nonlinearity-causing signal-dependent timing of the PWM pulses. Theoretical analysis and Monto-Carlo simulations verifying the linearity of the proposed DAC are presented.
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Zhang et al. (2018) studied this question.
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