New Continuous-Time Multibit Sigma–Delta Modulators With Low Sensitivity to Clock Jitter

In this paper, new continuous-time sigma-delta modulators (SDMs) are proposed where the output of a multibit (MB) quantizer is digitally converted to a single-bit pulsewidth-modulated (PWM) signal at a higher rate. The PWM signal is then fed back to the input through a finite-impulse-response digital-to-analog converter (DAC). The proposed modulators are shown to be less sensitive to clock jitter than their equivalent MB SDM, while their amplifiers have similar speed and power requirements. Furthermore, the proposed modulators do not require dynamic-element-matching techniques in the feedback path because a mismatch of the unit elements in the MB DAC does not produce distortion nor increases the noise floor in the signal band.