LLM-Driven Verilog Generation and Verification for RISC-V Processor Design

Large language models (LLMs) are increasingly used in Electronic Design Automation (EDA) to write hardware description code. This paper reviews how LLMs generate and verify Verilog for a RISC-V processor datapath, a core topic in Computer Architecture and Organization. The review is built around the AI-driven logic synthesis framework of Astillero (2026), which applies graph neural networks, reinforcement learning, and large circuit models to gate-level design and names functional verification as a main obstacle to automated hardware generation. This paper examines the register-transfer level (RTL) stage that comes before that synthesis and asks whether the same obstacle appears there. The review finds that LLMs can often generate valid Verilog for small, well-specified modules, that they are expected to be less dependable for sequential and pipelined designs, and that verification remains a major challenge, which is consistent with Astillero's conclusion at the gate level. This paper proposes a workflow that combines LLM generation, simulation feedback, human review, and AI-driven synthesis with equivalence checking as a dependable approach.