Comprehensive Stability Analysis of Fully Transparent Low-Power Thin-Film Transistors: Role of Device Design and Electrical Parameters

This article states the simulation of a-IGZO (amorphous-indium gallium zinc oxide)-based thin film transistor (TFT) using the Silvaco-Atlas tool, which is operated at a low voltage of 1.5 V. In this TFT, ZrO2(zirconium dioxide) acts as a gate dielectric, and IZO (indium zinc oxide) is utilized as electrodes for the gate, source, and drain terminal. This simulated TFT exhibits excellent performance parameters such as a small threshold voltage (VTH) of 0.21 V, mobility (μn) of ~ 8.37cm2/V − s, a subthreshold swing (SS) of ~ 84mV/decade, and a high on-off ratio ~ 106. In addition to the estimation of performance parameters, the hysteresis curve is also evaluated for gate-source voltage (VGS), which varies from 0 to 1.5 V and the same in the reverse manner. The impact of different parameters, such as variable thickness of the dielectric layer, active layer, and different magnitudes of fixed charge density, is also observed in the plotting of the hysteresis curve and in the calculation of ΔVTH. From all the cases, it has been concluded that for an oxide thickness of 40 nm and an active layer thickness of 30 nm, the change is very small in ΔVTH, that is, 0.0003, 0.0015, 0.003, “0.006,” “0.009,” “0.016,” and “0.023 V” for stress times of “0 s,” “600 s,” “1200 s,” “1800 s,” “3600 s,” “5400 s,” and “7200 s.” The minimal variations in threshold voltage across different stress durations confirm the enhanced positive bias stress (PBS) stability of the a-IGZO low-voltage TFT device, highlighting its potential for future low-power and flexible electronic applications.