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January 1, 2010IEEE Journal of Solid-State Circuits

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits

Takahiro Irita Seiji Mochizuki Masakazu Ehama Motoki Kimura Jun Takemura Keiji Matsumoto Tadashi Teranuma Katsuji Takakubo Hiromi Watanabe Toshihiro Hattori

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Abstract

A full-HD (1080p30) 500 MHz mobile application processor with an H.264 HP/MPEG-2/MPEG-4 video codec is integrated on a6.4× 6.5\ mm²die in 65 nm low-power CMOS. With two parallel pipelines for macroblock processing and tile-based address translation circuits, the processor consumes 342 mW in real-time playback of a full-HD H.264 stream from a 64 b width low-power DDR-SDRAM at an operating frequency of 166 MHz at 1.2 V.

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Irita et al. (2010) studied this question.

synapsesocial.com/papers/6ac6dfdb487cef9a5c7cb918 https://doi.org/10.1109/jssc.2009.2031797

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