Further power and energy reductions via technology and voltage scaling have become extremely difficult due to leakage and variability issues. In this paper, we present a robust and energy-efficient computation architecture exploiting an asynchronous timing strategy to dynamically minimize leakage and to self-adapt to process variations and different operating conditions. Based on a logic topology with built-in leakage suppression, the prototype asynchronous neural signal processor demonstrates robust sub-threshold operation down to 0.25 V, while consuming only 460 nW in 0.03mm²in a 65 nm CMOS technology. These results represent a 4.4×reduction in power, a 3.7×reduction in energy and a 2.2×reduction in power density, when compared to the state-of-the-art processors.
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Liu et al. (2013) studied this question.
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