A sigma-delta digital/analog converter implemented in 0.6-/spl mu/ CMOS uses a 6-bit modulator together with a segmented noise-shaped scrambling scheme to achieve 113-dB A-weighted dynamic range over a 20-kHz bandwidth. A continuous-time output stage is used to achieve high signal-to-noise ratio in a 9.1-mm/sup 2/ die area. The output stage uses a dual return-to-zero circuit that eliminates errors caused by intersymbol interference.
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Robert W. Adams (1998) studied this question.
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