A stereo multibit ΣΔ DAC with asynchronous master-clock interface

A two-channel multibit /spl Sigma//spl Delta/ audio digital-to-analog converter (DAC) with on-chip digital phase-locked loop and sample-rate converter is described. The circuit requires no over-sampled synchronous clocks to operate and rejects input sample clock jitter above 16 Hz at 6 dB/octave. A second-order modulator with a multibit quantizer, switched-capacitor (SC) DAC, and single-ended second-order SC filter provides a measured out-of-band noise of -63 dBr with less than 0.1/spl deg/ phase nonlinearity. Measured S/(THD+N) of the DAC channel including a 0-63 dB, 1 dB/step attenuator is greater than 90 dB unweighted. The circuit is implemented in 0.6-/spl mu/m DPDM CMOS, dissipating 220 mW at 5 V. Die size is 3 mm/spl times/4 mm.