Nonlinearity correction of the integrated time-to-digital converter with direct coding

A method is presented for automated identification and correction of the nonlinearity error of the time-to-digital converter (TDC) with delay-line coding and 200 ps resolution, integrated on a single Field Programmable Gate Array (FPGA) device. The nonlinearity error is estimated using a statistical method based on a sufficiently large number N of measurements of random input time intervals having a uniform distribution within the input range of TDC. Then, the resulting estimate of the error function is used for training a two-layer neural network (NN) designed for correction of the nonlinearity error. Training of the NN is based on the fast Levenberg-Marquardt (LM) learning rule and the goal is to minimize the maximum nonlinearity error of the TDC. Experimental tests have shown, that using a relatively small number of N=5/spl times/10/sup 4/ identification measurements the maximum nonlinearity error of a TDC may be reduced from 1.37 LSB (least significant bit) to about 0.12 LSB (24 ps).