Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions

Attaining timing closure marks the culmination of an arduous VLSI design process. The targets set for timing closure and the time taken to achieve it can critically impact the success of a product in a highly competitive semiconductor market. Therefore, methodologies employed in VLSI design process are strategized to attain quick timing closure along with reasonable design metrics. However, at advanced process nodes, attaining timing closure becomes quite challenging. As a result, at advanced process nodes, innovative solutions are required to be incorporated in VLSI design processes, as well as in Electronic Design Automation (EDA) tools and technologies. In this review paper, we discuss timing closure problem explaining the root cause of its difficulty. We also explain traditional techniques that address timing closure problem. Furthermore, we highlight new challenges that appear at advanced process nodes and discuss solutions to these problems that are being employed or are proposed in literature.