Integer Codes Correcting Single Sparse-Byte Errors and Detecting Double Sparse-Byte Errors

Sparse-byte error-control codes were originally developed mainly for protecting wide-I/O semiconductor memories, whereas their application to communication systems has received considerably less attention. In communication receivers, sparse-byte errors may arise from self-synchronous descrambling as well as from various byte-oriented operations. In this paper, we propose a class of integer codes capable of correcting single sparse-byte errors and detecting double sparse-byte errors. The proposed codes are defined over integer rings and constructed with the help of a computer search. To assess their efficiency, the proposed codes are compared with linear codes having similar error-control capabilities. We also investigate the potential of the proposed codes for practical implementation on modern processors. For this purpose, we use an analytical model of an eight-core processor. The obtained results show that, at a processor clock frequency of 4.5 GHz, the considered 32-bit codes achieve a theoretical encoding throughput of 144 Gbps and a minimum theoretical decoding throughput of 57.88 Gbps. These results indicate that the proposed approach has potential to be applied as a software-based solution for error control in modern communication systems.