High‐gain and power‐efficient dynamic amplifier for pipelined SAR ADCs

A new power‐efficient dynamic residue amplifier for pipelined successive‐approximation‐register (SAR) ADCs is presented. A complementary input pair and a reference level detection technique are proposed to improve the performance of the dynamic amplifier. At a 400 MS/s sampling rate, the proposed amplifier achieves a gain of 16. The input referred noise is 57.2 μV and the total harmonic distortion is –57.1 dB. The power consumption of the proposed amplifier is 55.6 μW in 28 nm CMOS technology.