Hybrid AI-Driven Very Large-Scale Integration Floorplan Optimization Using Graph Neural Networks and Reinforcement Learning

Floor planning is an important design phase in Very Large-Scale Integration (VLSI) circuits, as it approximates the space of a chip according to the optimum layout of blocks and their interconnections. This process entails figuring out the locations, shapes, and size of components that make up a chip. Floor planning in VLSI is not an easy task considering that, a slight change in placement of the components can consumes a lot of energy and heat during processing of the signals inside the VLSI architecture. Thus, to propose a framework based on the Hybrid model comprised of graph neural networks and reinforcement learning methods in order to achieve optimized floor planning to reduce the heat and the size of the architecture. Initially, the benchmark GSRC floorset dataset with information about blocks, netlists and connectivity is taken into account. Then, the initial placement of blocks are processed by the Graph Neural Network (GNN) based on identifying the relations among the blocks, netlists and connectivity for all the components to make predictions for the placement of the components in the regions. These initially placed parameters are then optimized using the Deterministic Policy Gradient (DDPG) agent that progressively tries and refines component layouts to improve the floorplan. The optimization process also aims to minimize important parameters such as total area, wire length, power usage and timing delays. The agent advances the layout by refinement in a series of steps until the layout is optimized to such a high level of efficiency and optimization that it satisfies the design goals, and enhances overall performance. Proposed method gives wire length of 15.3080 µm, Area of 519 400.1250 µm2 and white space ratio of 0.5732% for n10 circuit respectively. The proposed system learns optimum floorplanning solutions automatically. Its flexibility to various design constraints improves its productivity and extrapolation to VLSI designs.