Performance Analysis of In-Memory Computing Static Random Access Memory Array for Neural Network

Modern AI systems require high-speed and energy-efficient computation, yet traditional von Neumann architectures suffer from significant latency and power overhead due to continuous data transfers between memory and processing units. These limitations become more critical in neural-network and few-shot learning workloads, where rapid similarity computation is essential. To over- come these bottlenecks, we propose an In-Memory Computing (IMC) SRAM Macro that integrates L1 distance calculation and Winner-Take-All (WTA) operations directly within the memory array, effectively eliminating data-movement delays. The proposed architecture is implemented on a PYNQ-Z2 FPGA and validated using NGSPICE simulations. Experimental results demonstrate 20–30% improvement in speed, 10–15% higher power efficiency, and 5–10% reduction in area compared to traditional von Neumann-based designs. Additionally, the system achieves 27.7 TOPS/W energy efficiency and 99.34% accuracy in 5-shot learning. The integration of charge-based L1 distance computation and a low-latency WTA circuit within the SRAM macro provides a compact, scalable, and energy-efficient solution for real-time edge AI applications.