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An area-efficient low-power and low-latency 550-MSample/s FIR filter for magnetic recording read channel applications is presented. A parallel direct type II architecture operates on real-time deinterleaved (even and odd) input data samples and employs a fast low-area multiplier based on selection of radix-8 premultiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. The chip has been fabricated using a 0.18-/spl mu/m L-effective CMOS technology and is currently being used in commercial applications.
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Staszewski et al. (2000) studied this question.
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