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It has been shown that the same avalanche transistor can generate both short (8A/2 ns) and longer high-current pulses (90 A/7 ns), but the operating perimeter length self-organized by the transistor is much smaller in the first case (∼0.1 mm) than in the second (1.6 mm). Since the two-dimensional approach failed to explain this experimental fact, we present here an interpretation using quasi-three-dimensional modelling. Spatial triggering inhomogeneity should not exceed ∼5% for the transistor to survive when generating long pulses, while the same moderate inhomogeneity ensures short-pulsing operation because powerful current filamentation quenches the switching in the rest of the perimeter.
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Duan et al. (2012) studied this question.
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