From Heuristics to Learning a Review of AI Methods for Logic Gate in EDA

Description This review paper examines how Artificial Intelligence is changing logic gate synthesis in Electronic Design Automation (EDA). Classical heuristics such as Karnaugh maps, Quine-McCluskey and AIG rewriting struggle to scale to circuits with billions of gates, especially when balancing power, performance and area (PPA). The paper builds on Astillero's study of AI-driven synthesis and organizes the field around three model families: Graph Neural Networks (GNNs): these represent circuits as directed graphs and estimate delay, power and congestion before physical routing. Reinforcement Learning (RL): agents learn sequences of rewrite operations on And-Inverter Graphs (AIGs) and Majority-Inverter Graphs (MIGs) that greedy optimizers miss, guided by a combined area, delay and power reward. Large Circuit Models (LCMs): transformer models that translate specifications or HDL directly into gate-level netlists. The paper compares these methods with traditional flows across five dimensions: optimization strategy, PPA exploration, scaling, parasitic awareness and adaptability across technology libraries. It then covers three applications: approximate computing, SAT sweeping and equivalence checking, and automated CPU/ASIC generation. It concludes that data scarcity and the lack of guaranteed functional correctness are the main barriers to adoption. It argues that closing the loop between generation and formal verification is the key research priority.