Impact of side-recess engineering on electrostatic control, carrier trapping, and high-frequency performance of InGaAs metamorphic HEMTs

In this study, we explore the influence of the side-recess length (L side ) on the DC, pulsed I-V, RF, and RF noise characteristics of InGaAs metamorphic high-electron-mobility transistors (mHEMTs) on GaAs substrates. Devices with different side-recess lengths of 70, 95, and 120 nm were fabricated by varying the recess etching time to 35, 45, and 55 s, respectively. As L side increases, drain current decreases because the extended recessed access region increases the parasitic source/drain resistance, whereas electrostatic gate control is enhanced owing to suppressed short-channel effects and reduced electrostatic coupling at the drain-side access region. Pulsed I-V measurements reveal that the devices with wider L side exhibit more pronounced gate-lag, consistent with an increased contribution from surface-related trapping in the wider exposed recess region. Nevertheless, the device with the widest L side achieves the highest f max of 472 GHz and the lowest minimum noise figure (NF min ) below 0.75 dB over the K/Ka-band (18–40 GHz), accompanied by increased g mi and reduced g ds at the noise-bias condition. These results demonstrate that side-recess engineering governs a fundamental trade-off among electrostatic integrity, access resistance, surface trapping, and RF performance, providing a practical design parameter for optimizing InGaAs mHEMTs according to application-specific requirements.