Low-Power Area-Efficient LDO With Loop-Gain and Bandwidth Enhancement Using Non-Dominant Pole Movement Technique for IoT Applications

A new Low Drop-Out (LDO) voltage regulator with off-chip capacitor for low power applications is presented. The LDO takes advantage of non-dominant pole movement technique to improve loop-gain and Unity Gain Frequency (UGF). Tangible improvements were obtained while supporting a large load capacitor and low-power consumption. The proposed LDO 1) consumes low quiescent current (47.3% current efficiency (CE) at 10 μA load current bias circuit inclusive), 2) is area-efficient (no multi-gain amplifiers), and 3) enjoys a short response time in the active-mode with its adaptive bandwidth expansion and loop-gain enhancement technique, while 4) maintaining 99.94% CE in the full-load condition. A prototype chip with TSMC 180 nm CMOS technology was fabricated for detailed characterisation. The measured output voltage of the LDO was 1.65 V with 1.8 V input, consuming 11 μA quiescent current including the bias circuit current. The load regulation was 10 mV when load current changes from 30 nA to 50 mA with fall and rise time of 10ns.