High-speed FPGA implementation of the CORDIC algorithm using carry lookahead adders

This paper presents an efficient hardware architecture for sine and cosine generation using the CORDIC (Coordinate Rotation Digital Computer) algorithm. The design employs a pipelined scale-free CORDIC datapath integrated with a carry look-ahead adder (CLA) to reduce critical path delay and improve computational speed compared to conventional ripple-carry adder (RCA) implementations. To achieve an optimal balance between performance and hardware cost, hybrid CLA–RCA configurations are introduced, where CLAs are selectively used in timing-critical stages while RCAs are retained in non-critical paths. Furthermore, mutually exclusive micro-rotation techniques are utilized to reduce the number of iterations and eliminate the need for scale-factor compensation, thereby enhancing efficiency. The proposed architecture is implemented and synthesized on both FPGA and ASIC platforms to validate its performance and portability. FPGA implementation on Xilinx Artix-7 confirms accurate sine and cosine outputs with low power consumption of 0.175W, while a standard-cell ASIC realization on the open SkyWater 130 nm (Sky130) PDK using the Yosys–OpenROAD flow further demonstrates a core area of \(0.88 mm²\) , an achievable clock frequency of \(32 MHz\) , and a total power of \(10.2 mW\) , confirming successful timing closure with zero violations across all sign-off corners.