VLSI Implementation of CSD Based Efficient FIR Filter for ECG Signal Denoising

This paper presents a novel hardware-efficient Canonical Signed Digit Finite Impulse Response Filter pipelined (CSD-FIR-P) architecture using an XOR-MUX-based adder in tree topology. In this paper hardware sharing is proposed to remove the redundant computation that leads to the minimization of logic sources. Also, from the statistical analysis presented for the HDL coder coefficient and traditional CSD coefficients, it's evident that the traditional CSD coefficient is proven efficient in hardware complexity. The proposed CSD-FIR-P filter with XOR-MUX-based adder architecture is multiplier-less and is shown to be more efficient in terms of hardware utilization, area, power, and delay than conventional methods. This proposed CSD-FIR-P architecture for filter operation is applied for the ECG de-noising process. Thus the suggested FIR filter is then implemented with hardware sharing traditional CSD coefficients through Matlab to provide an effective solution (coefficients) using Verilog HDL for VLSI, with the synthesis of ASIC (180 nm technology) and FPGA (Kintex -7 xc7k70tfbv676-1 family) done with Xilinx Vivado and Cadence Genus, respectively.