GPS-Synchronized System for FPGA-Based Acceleration Measurement

This paper proposes an autonomous, resource-efficient, FPGA-based synchronization architecture for distributed accelerograph networks. Unlike existing FPGA implementations that focus primarily on acceleration acquisition, the proposed design integrates GPS-disciplined synchronization, synchronized acceleration acquisition, and real-time synchronization error estimation on a single FPGA platform, enabling autonomous sensing nodes without centralized clock distribution. The architecture was evaluated under various weather conditions, demonstrating reliable performance in real-world deployments. The architecture uses the Global Positioning System (GPS) one Pulse-Per-Second (1PPS) signal as the timing reference and integrates a Digital Phase-Locked Loop (DPLL), two frequency dividers, and a synchronization error estimation module. The DPLL generates a 1.024 MHz master clock, from which a 1 kHz sampling signal (Ext_Sync) and a synchronized 1 Hz signal (Ext_1Hz) are derived. The design was implemented in VHDL and Verilog, synthesized on a Cyclone V 5CSEBA6U23I7 FPGA, and experimentally validated on a DE10-Nano development board. The design was evaluated through hardware synthesis, synchronization accuracy under three weather conditions (cloudy, moderate rain, and clear sky), acceleration measurements, frequency-response characterization, and statistical analysis using analysis of variance (ANOVA). The proposed architecture achieved a mean synchronization error of 4.07 µs. Furthermore, the measured frequency response satisfied the requirements of the International Society of Explosives Engineers (ISEE) over approximately 40% of the specified frequency range, demonstrating the feasibility of the proposed architecture for synchronized accelerograph networks in scientific instrumentation and seismic monitoring applications.