A Pipelined FPGA-Based Frame Synchronizer for Gaussian Noise Channels

This paper presents a Field Programmable Gate Array (FPGA)-implementable Frame Synchronizer that overcomes deficiencies of existing synchronizers in the space communications industry and provides a pipelined approach to achieve improved performance in latency, performance in the presence of noise, and streamlined implementation complexity. Unlike a soft decision synchronizer, magnitude (soft) bits are not required from the demodulation stage, and only the sign bit is used, reducing the complexity and signal counts between the transceiver and the synchronizer. Improved performance in noise can be achieved by introducing a small observation window surrounding the candidate Attached Sync Marker (ASM) window to uncorrelated data around the ASM. Further improvement in the presence of noise is achieved by using two ASMs, effectively doubling the ASM length of observation, but with no increase in the ASM pattern length and using existing predefined ASM patterns, thus remaining compliant with the Consultative Committee for Space Data Systems (CCSDS) standards. A parallel and pipelined implementation without a state machine eliminates latency from search, verify, lock, and flywheel states and reduces the effects of cycle slips of traditional flywheel state machine synchronizers.