Design Optimization of Slab Width for High-Performance Silicon PN Junction Modulators

In this paper, the structure of the silicon modulator is optimized by asymmetric slab design to enhance overall performance. Recognizing the inherent disparity in electron and hole mobilities in silicon, we propose and systematically investigate asymmetric slab designs where the n-type slab width is varied relative to the p-type slab. We demonstrate that optimally scaling the n-type slab width to 2.8 times that of the p-type slab effectively synchronizes the charging/discharging dynamics of the PN junction. This optimized design achieves a significant bandwidth enhancement to 35.73 GHz, a 3.01 GHz increase over the conventional symmetric design. Crucially, this performance gain is attained while maintaining comparable modulation efficiency and reducing optical loss. Finally, the asymmetric slab structure proposed in this paper is applicable to almost all PN junction devices.