Accurate electrothermal parameter extraction is essential for compact modeling of gallium nitride on silicon carbide (GaN-on-SiC) high-electron-mobility transistors (HEMTs) used in radio-frequency (RF) and high-power circuits. This study compares four published compact drain-current formulations: the Fager-Pedro LDMOS model, the Yang model, the Curtice cubic model, and the Cao enhanced EEHEMT model. We fitted each formulation to room-temperature, on-wafer direct-current (DC) current-voltage (I-V) measurements from devices with total gate peripheries of 1, 2, and 4 mm. We used African Vulture Optimization (AVO), Multi-Trial Differential Evolution (MTDE), the Enzyme Action Optimizer (EAO), and the Equilibrium Optimizer (EO) to extract the electrical and effective thermal parameters. We evaluated each result using mean squared error (MSE) and physical-plausibility checks, including the expected decrease in effective thermal resistance with increasing device periphery. The Fager-Pedro model produced the lowest errors for the 1 and 4 mm devices, whereas the Cao enhanced EEHEMT model gave the best result for the 2 mm device. The Curtice cubic model generally represented the largest device more accurately than the Yang model. EO gave the lowest runtime in the benchmark test, while MTDE achieved the minimum fitting error in most cases, although the optimizers used different computational budgets. These results provide a comparative workflow for selecting drain-current formulations and parameter-extraction strategies for GaN-on-SiC HEMTs. The conclusions are limited to room-temperature, steady-state DC measurements and require validation under pulsed, transient, and large-signal RF conditions.
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Uddin et al. (2026) studied this question.
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