A 24.5 dB Gain, 4.5–36.7 GHz Wideband 28‐nm CMOS LNA With Shunt‐Peaked Sequential Topology for Satellite Receivers

This article presents a 4.5–36.7 GHz low‐noise amplifier (LNA) fabricated in a commercial 28‐nm CMOS process for multi‐band satellite communication. To overcome the gain‐bandwidth limitation of conventional wideband LNAs, a Shunt‐Peaked Sequential (SPS) topology is proposed and integrated with a common‐gate (CG) amplifier, in which a Darlington‐based sequential transistor pair, a Peak‐Stabilization Loop (PSL), and an Impedance‐Coupled Matching Network (ICMN) are combined into a unified architecture to simultaneously enhance gain, extend bandwidth, achieve wideband impedance matching, and reduce power consumption. The proposed LNA achieves a peak gain of 24.5 dB, while both S11 and S22 remain below −10 dB throughout the operating band, with average values of −13.3 dB and −12.7 dB, respectively. The average noise figure is 4.1 dB. The IP1dB, OP1dB, IIP3, and OIP3 are −22.9 dBm, −4.2 dBm, 0 dBm, and 18.7 dBm, respectively. The proposed LNA consumes 12.2 mW, occupies a die area of 0.948 mm 2 , and achieves a competitive FoM of 24.51.