Next-Generation Zero-Server Edge Electronic Design Automation

Circuit simulation in Electronic Design Automation (EDA) must balance circuit models, numerical meth- ods, and hardware resources. Traditional SPICE- like tools assemble circuit equations using Modified Nodal Analysis (MNA), then obtain numerical so- lutions through nonlinear iteration, transient inte- gration, and sparse matrix solvers. Their strengths are mature models and traceable results; their costs are the memory and computation time required by large netlists. The basic idea of Edge Web EDA is to let users launch interactive circuit analysis in a browser and delegate part of the computation to WebAssembly and WebGPU. This direction is technically plausible: WebAssembly provides a portable execution envi- ronment near native performance, WebGPU pro- vides general-purpose compute shaders, and regu- lar operations such as sparse matrix-vector multi- plication have parallelization potential. However, the WebGPU core does not provide ready-made CSR, CG, LU, or SPICE solvers; nor can WGSL currently be treated as a universally available native double- precision environment [12, 13]. The main conclusion is that Edge Web EDA is suitable as an auxiliary layer for early design ex- ploration, parameter sweeps, teaching, and real- time visualization. It should not claim to re- place transient SPICE or tape-out sign-off compre- hensively without reproducible benchmarks, inde- pendent high-precision reference solutions, real- istic process models, and measurement compar- isons. Mixed-precision iterative refinement, PINNs, and FNOs may all provide speed advantages within clearly defined validation domains, but their cor- rectness and generalization must be assessed jointly using condition numbers, residuals, forward error, unseen topologies, and extreme operating condi- tions. This monograph also argues that “zero-server” should not mean that no backend or infrastructure exists at all. It should mean that, in a specified op- erating mode, the principal data and computation can remain on the user’s device. Sensitive PDKs, complete sign-off, and large simulations may still re- quire controlled servers or a cloud-edge collabora- tion architecture. Keywords and Verification Policy Keywords: Electronic Design Automation, SPICE, MNA, DAE, WebAssembly, WebGPU, sparse matri- ces, mixed precision, iterative refinement, PINN, FNO, WebNN, PDK