Cloud-Edge Hybrid Electronic Design Automation: Web- Based Circuit Placement, Cloud GPU Execution, and Zero-Trust IP Protection

Electronic Design Automation (EDA) faces a structural tension between interactive accessibility, computational scale, and intellectual property (IP) security. Traditional SPICE-class simulators [1, 4] execute on centralized on-premises Linux servers, providing high double-precision ( fp64 ) numerical fidelity but imposing rigid hardware provisioning costs and batch-mode turnaround delays. Conversely, pure client-side Edge Web EDA [35] leverages WebAssembly [5] and WebGPU [12] for zero-server interactive exploration, yet remains bounded by client memory limits (4 GiB in wasm32 , ~16 GiB practical in wasm64 [7]), missing native fp64 shader types in core WGSL [13], and the unacceptability of transmitting cleartext foundry Process Design Kits (PDKs) to untrusted user browsers [31, 34] This monograph investigates a third architectural paradigm: Web-Placed, Cloud-GPU-Executed EDA. In this model, the web browser functions strictly as a schematic capture, layout placement, and visual telemetry thin client, while circuit flattening, nonlinear Modified Nodal Analysis (MNA) evaluation [], and sparse matrix factorization execute exclusively on cloud-hosted enterprise GPUs equipped with native Tensor Cores and High-Bandwidth Memory (HBM3/HBM3e) [, ]. We evaluate five core engineering dimensions: (1) architectural feasibility across DC, transient, and post-layout parasitic workloads; (2) zero-trust IP and PDK protection via View-Only Schematic Abstraction, Hardware Trusted Execution Environments (TEEs) [], and server-side pixel/decimated waveform streaming; (3) the three primary engineering bottlenecks—wide-area network (WAN) round-trip latency, multi-gigabyte waveform bandwidth explosion, and cloud GPU idle cost—alongside their mathematical mitigations; (4) quantitative compute and memory scaling differentials between consumer browser WebGPU endpoints and data-center GPUs; and (5) a balanced pros-and-cons assessment and reproducible build roadmap.2fp64 233637