A Systematic Review and Comparative Analysis of Floating-Point Divider Architectures for High-Performance and Energy-Efficient Computing

Floating-point division remains one of the most computationally intensive operations in modern digital systems, significantly influencing latency, power consumption, and hardware complexity within floating-point units (FPUs). Its implementation typically relies on iterative quotient generation or reciprocal-based techniques, along with strict IEEE-754 compliance, making divider design a complex multi-objective optimization problem. This paper presents a systematic review of floating-point divider architectures, analyzing 58 representative studies published between 2004 and 2025. A structured taxonomy is developed to classify existing approaches into digit-recurrence, multiplicative (Newton–Raphson and Goldschmidt), approximate, Vedic, adaptive, and application-specific architectures. A unified evaluation framework is used to compare these designs across key performance metrics, including latency, throughput, power consumption, hardware area, numerical accuracy, and configurability. The principal contribution of this review is a unified, quantitatively grounded comparative framework that integrates the findings reported across the six architectural categories into measured or reported latency, power, area, and accuracy figures drawn directly from the primary literature, rather than qualitative description alone. The analysis shows that no single architecture achieves optimal performance across all criteria. Multiplicative methods offer high throughput and low latency, while digit-recurrence techniques ensure robustness and strict IEEE-754 compliance. Approximate and adaptive architectures improve energy efficiency and resource utilization, making them suitable for emerging domains such as artificial intelligence and edge computing. The study further identifies research gaps, including limited hybrid integration, insufficient workload-aware adaptability, and inconsistent benchmarking practices, and outlines future directions toward adaptive, hybrid, and application-aware divider architectures.