Topology-optimised near-chip microfluidic cooling for high power electronics

As front-end transistor scaling slows, advanced packaging approaches such as 2.5D/3D integration and co-packaged architectures are making thermal management an increasingly important package-level design challenge. In this scenario, cooling structures must be realised within package footprint and stack-height constraints to reduce thermal resistance and increase the cooling efficiency. Building on a previously developed direct-to-package serpentine microfluidic concept, this study applies density-based topology optimisation to redesign the coolant path in a manufacturable co-packaged microfluidic substrate while applying targets on peak temperature, temperature variance, and pressure drop. Numerical comparison with the baseline model shows that the optimised design reduces the total thermal resistance by 13.4% at 0.2 ml/s and 9.6% at 0.1 ml/s, and average pressure drop by 55% across all flow rates, demonstrating simultaneous thermal and hydraulic improvement within a practical packaging platform. Experimental evaluation on a thermal test chip further demonstrates a maximum power dissipation density of 753.1 W/cm 2 over the heater area, together with up to 17% lower convective thermal resistance. The optimised system also reaches a peak coefficient of performance of 13,923. These results show the potential of optimising the co-packaged microfluidic cooling substrates and support their use in future high-power package-integrated electronic systems.