Investigation and compact modeling for GIDL-assisted erase transients of metal gate 3D NAND flash memories

This paper presents a compact model for gate-induced drain leakage-assisted erase transients in metal-gate 3D NAND flash memories. The proposed model incorporates key physical mechanisms, including hole injection, electron back-tunneling, and pure tunneling electron emission. The model is implemented in SPICE to support string-level simulations involving multiple memory cells. Analytical electrostatic solutions are derived using 1-D cylindrical Poisson equations, enabling field-dependent current modeling across the O/N/O stack. The impact of gate work function (WF) on erase performance and speed is systematically investigated. Carrier injection timing analysis via technology computer-aided design (TCAD) reveals asymmetric behavior between hole and electron injection, emphasizing the necessity of modeling both mechanisms. Furthermore, a time-dependent capture ratio is introduced to bridge the discrepancies between TCAD and compact models. The proposed model shows strong consistency with reference TCAD results across various WFs and time scales, offering a physics-based phenomenological framework for circuit-level erase modeling in advanced 3D NAND architectures.