Oracle-Exact FPGA Execution of a Constraint Physical Computing Probability Controller: Architecture, Independent Validation, and Reproducible Hardware Evidence

We report a bounded physical validation of a deterministic classical probability and pseudorandom-number-generation controller developed within the Constraint Physical Computing (CPC) validation programme. The system couples an iCE40UP5K field-programmable gate array to an RP2040-based host interface using a 16-bit half-duplex data bus. An immutable, independently specified wire-level oracle serves as the comparison authority. In three recorded physical sessions, each comprising a SEED request and a subsequent PROB request, all six response frames matched the selected oracle frames word for word: 132 received 16-bit response words in total. The retained audit also checked six request and six response checksums, 18 FIFO snapshot hashes, protocol sequencing, received-word shadow comparisons and firmware-reported terminal states. A version-pinned public evidence subset provides the frozen fixtures, selected byte-preserved host transcripts, cryptographic manifests, a read-only verifier and corruption-rejection tests. The validation is deliberately bounded: the public verifier reproduces the reported record checks but does not independently attest electrical signals, installed fabric contents or the original physical acquisition. A previously observed unseeded transaction remains nonconformant to the immutable oracle, and full-corpus physical conformance is not established. These results constitute reproducible evidence for a classical digital CPC component, not quantum computation, native dissipative constraint solving or scalable Shor factorization.