A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic

This letter presents a 12-bit 180-MS/s pipelined-SAR ADC in 65-nm CMOS. To eliminate the complex interstage gain-error calibration for fast-response characteristic, a high-gain residue amplifier (RA) featuring a 2-stage gain-boosting architecture is proposed. By removing the tail current, the RA significantly alleviates slew-rate and voltage headroom limitations. The pre-amplifier incorporates a polarity-aligned CMFB technique that minimizes Miller capacitance while implementing a non-inverting feedback loop, thereby eliminating the conventional auxiliary inverting amplifier. Furthermore, a hardware-efficient asynchronous SAR logic based on an improved 6-transistor TSPC-DFF is developed to reduce power and shorten logic path. The prototype ADC achieves 64.5-dB SNDR and 81-dB SFDR at Nyquist input, while consuming 3.7 mW from a 1.2-V supply.