A platform-evidence mapping for DAL-B certification planning on an AMD64 multi-core processor with Xen temporal isolation

Civil-avionics multi-core integration is regulated by DO-178C and FAA Advisory Circular AC 20-193 with its EASA counterpart AMC 20-193, all of which require the applicant to identify and bound multi-core shared-resource interference. On the AMD64 reference configuration considered here, the shared last-level cache (LLC) is the interference channel analyzed in detail, and hardware way-partitioning alone does not bound the hypervisor’s own LLC footprint. The assumed platform is a Type-1 static-partitioning Xen configuration on AMD64 that uses Xen temporal isolation together with LLC cache coloring across guests and the hypervisor itself. Combined with the publicly-documented Xen safety-certification program as hypervisor-element evidence and a lean, model-based DO-178C / DO-331 workflow for hosted applications, the argument provides a candidate platform-evidence structure for a DAL-B applicant program, subject 1 to authority concurrence, program-specific timing closure, COTS hardware assurance , and hosted-application DO-178C evidence. We give objective-by-objective coverage for AC / AMC 20-193 and the multi-core-touched subset of DO-178C Annex A; identify DAL-A gaps; and ground the argument in a concrete UAS partition configuration. The certification mapping presented here is one input to an applicant program’s certification package; authority concurrence and hosted-application DO-178C evidence remain program responsibilities.