Digital Fault Detection and Self-Healing Circuit

Modern digital circuits may experience faults due to aging, manufacturing defects, voltage fluctuations, and environmental disturbances. Conventional systems can require manual diagnosis and intervention, which may increase downtime. This paper presents a Digital Fault Detection and Self-Healing Circuit designed using Verilog Hardware Description Language (Verilog HDL). The proposed architecture contains a primary processing unit, a backup processing unit, a fault detection module, a Finite State Machine (FSM) controller, and a multiplexer (MUX). The fault detection module monitors system status. When a fault is detected, the FSM controller activates the backup processing unit, and the MUX selects the backup output. During fault-free operation, the primary processing unit remains active. The design is intended to improve system reliability and support continued operation when a detected fault occurs. Xilinx Vivado is identified for design, synthesis, and simulation, while ModelSim can be used for additional simulation and waveform inspection. Actual fault-detection accuracy, recovery time, hardware overhead, and reliability improvement must be evaluated through testbench simulation and, where applicable, hardware measurements.