Simulation study demonstrates bio-inspired perceptron logic circuits maintain accuracy under faults while reducing area and power, suggesting a scalable alternative to triple modular redundancy.
Apart from energy limitations, a significant challenge in nano-scale integrated circuit design is the growing number of ’soft errors’ in computing systems caused by high-energy cosmic particles. Digital circuits with fault tolerance are more reliable in safety-critical applications such as embedded systems, medical equipment, aircraft, and satellite systems. Bio-inspired computing has significantly influenced advanced fields such as neuromorphic computing, computer vision, DNA computing, and cellular automata. In this context, the present work introduces a bio-inspired framework designed to achieve fault tolerance in digital circuits. The traditional fault-tolerant logic designs typically depend on hardware redundancy and error correction methods, which are resource-intensive. In this work, bio-inspired perceptron-based fault-resilient logic gate designs and their VLSI implementations are presented. By leveraging the adaptability and self-learning capacity of neural networks, our approach trains a perceptron to emulate essential logic functions (AND, OR, NOT, XOR) while dynamically adjusting the faulty gate behavior. The fault-tolerance capability of the proposed design is verified using the Vivado simulator by injecting faults at the input node. Results show that the proposed fault-resilient gates produce functionally equivalent outputs even under faulty input scenarios. Arithmetic units like full adder, multiplier, and sequential circuits are also trained, modeled, and synthesized in both FPGA and ASIC platforms. The synthesis results show a reduction in terms of area and power compared to the conventional Triple Modular Redundancy (TMR) system. The fault-resilient multiplier built using these fundamental blocks achieves area and power savings of 55.8% and 39.51% respectively. This method provides a scalable, bio-inspired framework for developing robust, self-adaptive digital circuits that tolerate faults at the input nets, making it well-suited for mission-critical and high-reliability applications.
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M et al. (2026) studied this question.
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