Enhancing Fault Detection in Digital Circuits Using Machine Learning and LFSR-Based Test Pattern Generation

For digital circuits, such as half adders, full adders, and other combinational logic gates, to be reliable, fault detection and test pattern creation are essential. This work introduces a novel method for effectively detecting faults in logic gates by combining machine learning (ML) with test pattern creation based on Linear Feedback Shift Registers (LFSR). Traditional methods for generating deterministic test patterns can be laborious and might not translate well to intricate circuits. In order to solve this, we use fault-injected datasets to apply a Random Forest Classifier (RFC) to categorize faults like Stuck-at-0 (SA0) and Stuck-at-1 (SA1). Comprehensive fault analysis is made possible by the LFSR-generated test patterns, which are inputs to circuits such as half adders and full adders. With a loss function of less than 1% and an R2 score of 99%, the trained ML model detects defects with accuracy. For complicated digital circuits, the combination of ML and LFSR-based test generation improves fault coverage, lowers computational overhead, and offers an effective Design-for-Test (DFT) method.