Model-Based Quantized Edge Vision Inference: Component Detection System for the STM32N6 Circuit Diagram

Against the backdrop of the rapid development of Edge AI, deploying object detection models on resource-constrained microcontrollers (MCUs) presents simultaneous challenges in terms of computing power, memory, and accuracy. This paper proposes an improved algorithm for detecting components in circuit diagrams and deploys it on an STM32N6 edge device. At the algorithmic level, using YOLOv8n as the baseline model, the study addresses the characteristics of circuit diagram components—which are extremely small and often arranged horizontally or vertically—by introducing an NWD-SIoU joint loss function to replace the default CIoU loss, thereby providing stable gradient signals and directional alignment for tiny objects.Additionally, Dropout regularization is incorporated into the detection head structure of YOLOv8n to address overfitting in circuit diagram training scenarios. Compared to the original algorithm, the improved algorithm achieves a 0.036 increase in F1-score, with precision and recall improving by 0.017 and 0.031, respectively. At the deployment level, post-training quantization from FP32 to INT8 was completed, reducing the weight size from 12 MB to 3.23 MB. To address the limited SRAM capacity of the STM32N6, a heterogeneous storage hierarchy allocation scheme was designed: static weights are stored in external Flash, while runtime activation tensors are locked in the NPU’s dedicated RAM. This approach frees up SRAM capacity while accelerating model execution. Experimental results demonstrate that the proposed approach achieves a balance of size, accuracy, and speed on the STM32N6 platform. It validates the feasibility of running complex vision models on edge devices and provides a reusable technical path for the implementation of edge AI in the field of industrial vision inspection.