Study on the Low-Power Transient Current Behavior in Scalable MIS Tunnel Diodes by Gear-Shaped Coupling Gate and High--Low Oxide Structures

Metal–insulator–semiconductor tunnel diode (MISTD) transient memory with designed coupling gates and high–low (HL) oxide structures was presented for capacitor-less dynamic memory. It was found that the quintuple gear-embedded arched structure reduces the device area by approximately 85% compared with the conventional concentric-circle structure and increases the transient memory window to about 104. This improvement is attributed to enhanced fringing electric fields at the high-curvature gear edges and the spatial concentration of process-induced oxide charges, which strengthen lateral carrier exchange. In addition, the dual-thickness HL oxide structure, featuring an inner-thick/outer-edge-thin dielectric profile, suppresses vertical tunneling leakage while maintaining lateral electrostatic coupling near the electrode edges. Multilevel cell (MLC) operation and reduced power consumption are also demonstrated, suggesting the feasibility of the proposed fully CMOS-compatible MISTD structure for dynamic random access memory (DRAM) applications.