Nanoscale thickness engineering of Y2O3 Carrier-Modulation layer for Simultaneous contact and reliability improvement in Sol-Gel processed crystalline In2O3/Y2O3 heterostructure transistors

High-mobility In 2 O 3 channel thin-film transistors (TFTs) are promising for emerging electronics, but simultaneously achieving desirable contact properties and stable operation remains challenging. We demonstrate that nanoscale thickness engineering of the Y 2 O 3 carrier-modulation layer (CML) optimizes contact performance and current-stress reliability in crystalline In 2 O 3 /Y 2 O 3 heterostructure TFTs. Transmission line measurements show that the CML thickness (t CML ) governs width-normalized contact resistance (R C W) and effective channel-length deviation (ΔL), with ΔL strongly suppressed at higher t CML . Under positive-bias stress (PBS), the threshold-voltage shift (ΔV TH ) decreases from 2.06 V at t CML = 1.0 nm to 0.58–0.80 V at t CML = 2.5–10.0 nm. Under current stress (CS), a thickness-dependent failure path appears. Although t CML = 2.5–5.0 nm maintains a low ΔV TH (0.75 V), t CML = 10.0 nm uniquely develops pronounced hump formation and severe μ lin degradation, along with non-monotonic maximum transconductance evolution. Systematic stress testing and electrical parameter analysis revealed that sustained current flow triggers stress-induced leakage current and percolation-assisted parasitic conduction, manifesting as an anomalous hump and trap-assisted soft-breakdown that may evolve into time-dependent dielectric breakdown. Overall, these results establish a practical nanoscale thickness window for CML design and emphasize the importance of considering CS for stable heterostructure TFT operation.