Power Optimized High Speed Sense Amplifier for 6T SRAM

Static Random Access Memory (SRAM) is used in a wide range of applications in modern VLSI like processors, microcontrollers, embedded systems and SoC due to its High Speed data access and reliable operation. A standard 6T SRAM cell is composed by 6 MOS transistors, two cross coupled inverters and two access transistors. While reading data there is a small voltage difference between complementary Bit Lines (BL and BL̅) which needs to be correctly sensed using a Sense Amplifier. Problems faced by traditional sense amplifiers can include increased levels of power consumption, slower sensing speeds and reduced reliabilities especially during low voltages. This project proposes a Power Optimized High Speed Sense Amplifier for 6T SRAM. The system uses a 6T SRAM Cell, Bit Line Precharging Circuit and Optimised Sense Amplifier. LTspice was used to create the design. The circuit was analysed by using transient waveforms of voltage and currents. Key parameters were looked at such as power consumption, speed and Read Delay. This should give us a fast data sensing circuit with reduced power consumption and reliable reading. The design would be useful for Low Power VLSI memory applications.