Monolithically integrated silicon photonic chip for broadband all-optical logic gates based on scattering metastructure

Integrated photonic computing offers high bandwidth and low latency for optical signal processing and optical neural networks (ONNs). We report a monolithically integrated silicon photonic logic-gate chip in which particle swarm optimization (PSO) inverse-designed scattering metastructures, thermo-optic phase modulators, amplitude modulators, and grating-coupler interfaces are implemented on a silicon-on-insulator platform. The optimized scattering cores realize AND, OR, and XOR operations in a 6 μm×6 μm region by mapping three coherent inputs to two output ports through multimode scattering interference. Equal-parameter Jacobian and singular-value analyses show that aperiodically distributed holes provide a higher-dimensional and directionally balanced local control space than regular trenches. Simulations at 1550 nm give minimum contrast ratios (CRs) of 7.8, 8.0, and 14.8 dB for the AND, OR, and XOR gates, respectively. Across 1540 to 1560 nm, the simulated CRs are typically above 5 dB and no lower than 3.7 dB. Fabricated and packaged chips reproduce the intended truth tables, with minimum measured CRs of 3.6, 7.8, and 15.4 dB, respectively. AND-gate measurements confirm correct operation across 1540 to 1560 nm and tolerance to a ±5 deg Bias-phase sweep, with measured insertion losses ranging from 5.56 to 12.49 dB. These results demonstrate feasibility for optical logic and ONN hardware.