Large Language Model-Based Bug Localization for RTL Designs Using Hierarchical Reasoning

The growing demand for sophisticated applications has driven a surge in circuit complexity, consequently raising the probability of design errors. This trend underscores the need for automated and effective debugging solutions. Large Language Models (LLMs) have shown strong analytical capabilities in program understanding and debugging, offering a novel perspective for bug localization in Register Transfer Level (RTL) designs. In this paper, we propose LocFree, a LLM-based framework for bug localization in RTL designs using hierarchical reasoning. LocFree comprises two main phases: the prompt generation phase and the bug localization phase. In the prompt generation phase, LocFree extracts four critical features from the Verilog code and its corresponding testbench: metadata feature, semantic structure feature, timing pattern feature, and testbench feature. It then employs these features in a hierarchical reasoning process to generates an optimized prompt that guides the LLM toward precise bug localization. In the bug localization phase, LocFree leverages the optimized prompt in conjunction with the LLM to identify the faults in the RTL designs. Experimental evaluation on 26 Verilog designs containing 397 bugs demonstrates that LocFree significantly outperforms state-of-the-art techniques. Specifically, our approach successfully localizes 76.8%, 82.5%, and 87.3% of bugs within the Top-1, Top-3, and Top-5 ranks, respectively—substantially exceeding the performance of existing bug localization methods.