Real-Time Analytical Selective Harmonic Elimination Method for CHB Inverters Using FPGA and NIOS II Processor

This study presents a real-time analytical approach to calculating switching angles in a multilevel inverter. The method determines a set of switching angles equal to s=2n that eliminate n harmonics and all their multiples from the output voltage waveform. To minimize computational complexity, the arccos function in the switching angle calculation is replaced by a cubic least-squares polynomial. Simulation analysis of various topologies, including 33-level single-phase and three-phase systems, demonstrates the effectiveness of the selective harmonic elimination algorithm. The experimental verification of the algorithm on 9- and 17-level single-phase and three-phase five-level systems using an Altera Cyclone V with an NIOS II soft-core processor is also presented. Furthermore, the dynamic behavior of the algorithm is evaluated through a closed-loop test on a nine-level topology.