Area–power–delay Optimized RTL-To-GDSII VLSI Implementation of 16-Bit Ve-Dic Multiplier Using High-Speed Adders

This paper presents a comparative analysis and an ASIC-oriented design of a 16-bit Vedic Multiplier based on the Urdhva-Tiryakbhyam algorithm using Kogge-Stone (KSA), Carry Look-Ahead (CLA), and Carry Save (CSA) adders. The architectures are implemented in Verilog HDL and evaluated across 45 nm, 90 nm, and 180 nm technology nodes using the Cadence suite. Pre-layout synthesis metrics (cell count, delay, and power) are analyzed to study performance trade-offs across nodes. Furthermore, physical design placement and routing at 90 nm confirms ASIC standard-cell feasibility, although detailed post-route parasitic extraction is reserved for future hardware prototyping. Comparisons with FPGA-based works demonstrate significant improvements in speed and power efficiency, making the proposed KSA-based design highly suitable for high-speed, low-power VLSI and DSP applications.