A SiC JFET With Buffer Layer Design: Short-Circuit Failure Mechanism and Robustness Enhancement

Emerging DC power distribution applications urgently require highly reliable silicon carbide (SiC) JFETs. Therefore, exploring structural reinforcement strategies for short-circuit robustness at the monolithic device level is of critical importance. In this paper, the microscopic short-circuit failure mechanism of SiC JFETs is thoroughly investigated using TCAD electro-thermal simulations, and an epitaxial buffer layer is proposed for monolithic structural reinforcement and parameter optimization. Simulation results demonstrate that the short-circuit evolution process can be systematically partitioned into three key physical phases: an initial mobility-dominated phase, an intermediate steady thermal equalization phase, and a late-stage intrinsic excitation surge phase. During the second and third phases, the dynamic space charge modulation effect within the SiC JFET causes the main peak electric field to collapse at the channel and transfer to the drift region/substrate interface. Consequently, the internal hot spot migrates accordingly, accelerating the global electro-thermal positive feedback. The introduction of a highly doped N-type epitaxial buffer layer effectively suppresses this failure path. Under high bus voltage conditions, utilizing an optimized buffer layer with a thickness of 4 μm and a doping concentration of 4×1017 cm-3, the maximum short-circuit withstand time is increased by 9.64%, reaching 590.1 μs. This improvement is attributed to the fact that the proposed structure delays the bottom-ward propagation of dynamic space charge in the second phase and significantly attenuates the peak electric field at the drift region/substrate interface in the third phase, thereby fundamentally delaying the onset of electro-thermal positive feedback.