The Partition Axis on Silicon: A Pre-Registered, Two-Core Correction of a Frozen Decision Token's Compute-Cost Map

The Partition Axis on Silicon: A Pre-Registered, Two-Core Correction of a Frozen Decision Token's Compute-Cost Map Randolph James Ferlic, M.D. and Kimberly Kate Ferlic — Fieldstone Analytics, LLC, Austin, TX, USA Preprint · Zenodo DOI: 10.5281/zenodo.24148008 · CC-BY 4.0 · Community: spiral-domain-encoder-campaign · a characterization of previously published methods that are the subject of filed U.S. patent applications, measured on commodity microcontroller silicon; it discloses no new algorithmic subject matter and is accompanied by no new patent application — see the notice below. Abstract A companion study established, on a desktop compute proxy, that the feature front-end — the partition axis — of a frozen, deterministic, single-token decision encoder is a recalibration-free amplitude-drift invariance lever, and it ranked the five axes by a wall-clock-per-window cost measured on an x86 host (channel 1× · ordinal ≈2× · frequency ≈5× · recurrence ≈70× · topological ≈81×), from which it drew a deployment contract: ordinal when cost-constrained, microcontroller-plausible; topological when accuracy is paramount at ≈80× compute. That cost claim rests on a host proxy and was explicitly labelled as such. Here we port all five front-ends to bit-faithful C and measure them on real microcontroller silicon — a Cortex-M4F (Nordic nRF52840) and a Cortex-M33 (Nordic nRF54L15) — under a pre-registered protocol with frozen Go/No-Go bands and a stop-if-it-does-not-sing deposit gate. The headline result is a correction: on silicon the cost ordering swaps at the expensive end. Where the desktop proxy ranks the topological axis costliest (81× the channel axis) and recurrence second (70×), the M4F ranks recurrence costliest by far (123×) and topological far cheaper (34×); the Spearman rank-correlation between the on-silicon and desktop orderings is 0.90, with the single inversion exactly the topological↔recurrence pair. The mechanism is the memory hierarchy a desktop proxy hides: the recurrence front-end is bottlenecked by an O(L²) distance matrix (~97 KB, cache-hostile) plus a 12,403-element quantile sort, while the topological front-end uses a matrix-free minimum-spanning-tree construction with no stored matrix and no sort. The correction is not a one-board artifact — the M33 reproduces the identical ordering (Spearman vs. the M4F = 1.00; vs. the desktop proxy = 0.90), and every one of twelve pre-registered hardening tiers (per-axis current, true-idle floor, 8-channel scale-up, a hardware FFT, a 1.8 V point, a picojoule-per-cycle cross-check, a linker-map footprint, a window-length sweep, and a data-robustness pass) confirmed or sharpened it. Measured/analytic energy pins a deployment-ready tier boundary: an always-on tier (channel, ordinal) that duty-cycles below 1 mW at 1 Hz, a mid tier (frequency), and an edge tier (topological, recurrence) in which topological only marginally exceeds the always-on budget at 1 Hz (1.09 mW) while recurrence runs far over it (2.73 mW) and is disqualified on compute and memory (~145 KB) and, uniquely, on determinism. A fourth, previously unmeasured axis dimension emerges on-device: the ordinal front-end is the only one whose entire raw→token path is bit-exact across a float64 host and a float32 device (0 of 64 flips), where the recurrence (6%) and topological (25%) front-ends inherit their features' floating-point sensitivity — so ordinal dominates not only on compute, energy, and memory but on auditability. A pre-registered second thesis — that the rank-based relational token is cross-precision portable where the FFT-based channel token is not — is reported as an honest negative: the relational feature vectors are exactly precision-invariant, but on FPU silicon the channel token is equally token-stable, so the property confers no token-level advantage. The practical consequence is a corrected deployment map: ordinal is the cheap invariant on real silicon, confirmed on two cores and in energy, memory, and determinism; topological is a mid-tier front-end on compute and memory, not an ≈80× luxury; and recurrence, not topological, is the axis to avoid on a microcontroller. This is a characterization, on commodity hardware, of previously published methods that are the subject of filed U.S. patent applications; it discloses no new algorithmic subject matter. The per-deployment axis-selection and commissioning procedure is retained as trade secret. Highlights · The on-silicon cost ordering corrects the desktop proxy. On a Cortex-M4F the partition axes' compute cost rank-correlates with the x86 proxy at Spearman 0.90, with one inversion: recurrence (123× the channel axis), not topological (34×), is the costly axis — the exact opposite of the proxy's topological-costliest (81×) / recurrence-second (70×) ranking. · The mechanism is the memory hierarchy. Recurrence is bottlenecked by an O(L²) distance matrix (~97 KB) and a 12,403-element quantile sort, both hostile to a cache-poor microcontroller; topological uses a matrix-free minimum-spanning tree with no stored matrix and no sort. A desktop proxy with a large cache mis-ranks exactly where cache and sort bite. · It is robust across two cores and every hardening tier. A Cortex-M33 reproduces the identical ordering (Spearman vs. M4F = 1.00); the recurrence↔topological swap holds on both. Twelve pre-registered hardening tiers — per-axis current, idle floor, 8-channel scale-up, a hardware FFT, 1.8 V, a pJ/cycle cross-check, a footprint pass, a window sweep, and data-robustness — each confirmed or sharpened the finding; none threatened it. · A measured energy tier boundary. An always-on tier (channel, ordinal) duty-cycles below 1 mW at 1 Hz; a mid tier (frequency); an edge tier (topological, recurrence). Both relational-heavy axes exceed the 1 mW budget at 1 Hz — topological only marginally (1.09 mW), recurrence by nearly threefold (2.73 mW) and over ~145 KB RAM — so recurrence is disqualified on compute, energy, and memory alike. · Determinism is a fourth axis dimension. The ordinal front-end is the only axis whose entire raw→token path is bit-exact on a float32 device versus a float64 host (0/64 flips); recurrence flips 6% and topological 25%. Ordinal dominates on compute, energy, memory, and auditability. · An honest negative, reported straight. A pre-registered cross-precision-portability thesis is refuted as a differentiator: relational features are exactly precision-invariant, but on FPU silicon the channel token is equally stable, so the property buys no token-level advantage. No new mechanism is introduced. The correction, in two measured tables On silicon the cost ordering swaps at the expensive end — recurrence, not topological, is the costly axis — and the Spearman correlation to the desktop proxy is 0.90, the single inversion being the exact topological↔recurrence pair the deployment contract turned on. The Cortex-M33 reproduces the identical ordering (Spearman vs. M4F = 1.00). axis M4F ×channel desktop proxy ×channel M33 ×channel channel 1.0 1 1.0 ordinal 1.9 2 1.7 frequency 11.0 5 12.0 topological 33.7 81 29.8 recurrence 123.0 70 104.2 Against a measured 0.47 mW idle floor, the per-axis energy pins an always-on / mid / edge boundary. Both topological and recurrence exceed 1 mW at 1 Hz — topological only marginally (1.09 mW), recurrence by nearly threefold (2.73 mW); topological — the proxy's "≈80× luxury" — is mid-tier on compute and memory on measured silicon, while recurrence is edge-only on every dimension. axis energy/window (µJ) avg power @1 Hz (mW) tier channel 19.0 0.488 always-on ordinal 35.7 0.504 always-on frequency 210.3 0.673 mid topological 641.1 1.088 edge recurrence 2342.9 2.727 edge The transferable lesson The value of a compute-cost map is bounded by the faithfulness of its proxy. For an always-on, sub-milliwatt primitive that lives on a cache-poor microcontroller, an algorithm's cost is set as much by its memory-access pattern as by its operation count, and a desktop host — with megabytes of cache and an aggressive memory subsystem — hides exactly the costs that dominate on-device. Here that gap was not cosmetic: the proxy's expensive end was backwards, ranking topological the costliest axis when on silicon recurrence costs nearly four times as much, because a desktop swallows recurrence's O(L²) distance matrix and quantile sort while a microcontroller thrashes on them. Measuring on the hardware the method targets did two things a proxy could not: it corrected the one quantity that carried the whole deployment contract, and it surfaced a dimension no desktop study can see — end-to-end determinism across the float64→float32 boundary, on which the integer-rank ordinal axis is uniquely perfect (0/64 flips) while the floating-point topological axis flips a quarter of its tokens. The durable reading for sub-milliwatt Tier-0 sensing is that the axis you can actually afford — and actually audit — is the cheap, rank-based invariant, and that you learn which axis that is only by measuring on silicon, not by estimating on a host. What this record contains A seventeen-section manuscript (PDF and editable DOCX; four figures — the cost-ordering swap, the cost/memory anatomy of static-RAM footprint and window-length scaling, the measured energy tier boundary, and the determinism bars) and a reproducibility archive (PAPER_73_ZENODO_ARCHIVE.zip, md5 in ARCHIVE_MD5.txt). The archive holds the five partition-axis C front-ends and the frozen token kernel (inference-only, no-malloc, no-OS C that compiles bit-faithfully for a host and both devices from one source), the bare-metal benchmark harness and per-tier runners, the two device linker scripts, the Power Profiler Kit II driver, and the offline gold