Hybrid Roll‐To‐Plate Printed CMOS Logic Circuits Via an Integrated Gravure‐Flexographic Printing Strategy

Printed electronics offer a scalable route to large‐area, low‐cost, and flexible electronic systems, but multilayer integration remains limited by differences in ink rheology, film formation, and patterning requirements across functional layers. Here, we present a hybrid gravure–flexographic Roll‐to‐Plate (R2P) printing strategy for fully printed single‐walled carbon nanotube (SWCNT) thin‐film transistors (TFTs) and complementary metal‐oxide‐semiconductor (CMOS) logic circuits. Instead of using a single printing method across the device stack, we assigned flexographic printing to the gate and drain‐source (D‐S) electrodes, while using gravure printing for the dielectric, SWCNT semiconductor, and doping layers. The ∼45 nm‐thick flexographic‐printed gate enabled a uniform gravure‐printed BaTiO 3 dielectric with a thickness of 1.8 ± 0.08 µm and an areal capacitance of 13.2 ± 1.2 nF cm − 2 . The resulting p‐ and n‐type SWCNT‐TFTs exhibited mobilities of 0.08 and 0.05 cm 2 V − 1 s − 1 , respectively. Flexographic D‐S printing also reduced threshold‐voltage variation, improving device uniformity for circuit integration. Using these complementary transistors, we fabricated a fully printed CMOS ring oscillator operating at 60 Hz and a D‐Latch at 5 Hz, demonstrating the potential of layer‐specific hybrid printing for scalable printed CMOS electronics.