A Compact Mathematical Model and Hardware Implementation of Spike-Frequency Adaptation for Low-Power Neuromorphic Computing

The ionic currents in biological neurons and the electron transport in MOSFET devices both exhibit nonlinear dynamics, enabling transistors to emulate neuronal spiking behavior. Transistor–capacitor networks form conductive pathways analogous to biological ion channels such asNa⁺,K⁺,Ca²⁺, andCl⁻, and generate membrane-like voltages and action-potential-like spikes. This paper formulates an interspike interval (ISI) equation inspired by calcium-activatedK⁺channel behavior, in which spike-frequency adaptation (SFA) currents translate adaptation mechanisms into subthreshold, CMOS-compatible circuit primitives, enabling intrinsic firing-rate self-regulation. The gradual increase in ISI metrics, measured from spikes, demonstrates SFA in the proposed neuron model. SPICE-based simulations that validate adaptive behavior, tunable firing-rate, and signal attenuation properties consistent with theoretical predictions. The simulation results show that the neuron consumes an average power of 15.23 nW and has an energy efficiency of 1.687 fJ/spike at a spike firing rate of 34.81 MHz, and 634.2 fJ/spike at a low spike frequency of 67.8 kHz due to adaptation, highlighting the modeling for CMOS neuron implementation. This approach emphasizes biological adaptive temporal dynamics, together with a variability-aware, low-power CMOS realization, suitable for future neuromorphic accelerator hardware.